In complementary bipolar complementary-metal-oxide semiconductor (BiCMOS) fabrication processes, bipolar devices and CMOS devices are integrated on the same semiconductor substrate. Complementary BiCMOS fabrication processes are flexible in terms of circuit design but can also be very expensive since they typically require several masking layers to enable both high performance NPN and PNP bipolar transistors on the same semiconductor substrate along with CMOS devices.
In one approach of complementary BiCMOS process flow, a complex process requiring a mask count in the range of approximately 40 to 50 masking layers is used to form SiGe heterojunction bipolar transistors for both NPN and PNP devices. In this approach, the process flow enables high performance devices but at a high cost. While this approach might be reasonable for low volume applications where higher wafer costs do not necessarily determine the economic feasibility of a given product, for high volume applications economic concerns dictate that the wafer cost be minimized as much as possible in order to enable a cost effective and profitable product. In another approach, a relatively simple process flow is used for co-implantation of an undoped silicon-germanium (SiGe) layer to form the bases of the NPN and PNP devices. Although, in this approach, cost is reduced but device performance is compromised by the lack of independently customized SiGe profiles for the bases of the NPN and PNP devices.
Thus, there is a need in the art for a complementary BiCMOS process for efficiently integrating complementary bipolar devices, such as SiGe NPN and PNP devices, with CMOS devices without undesirably increasing processing complexity and manufacturing cost.